// Copyright (C) 1953-2022 NUDT
// Verilog module name - mux_taux
// Version: V4.0.20221216
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//         mux_taux
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps

module mux_taux
(
	i_clk	,				
	i_rst_n	,			
	
	iv_command_ack_reg  ,   
	i_command_ack_reg_wr,   
	                       
	iv_command_ack_tab  ,    
	i_command_ack_tab_wr, 
	
	ov_command_ack      ,  		
	o_command_ack_wr 		
);
input 				i_clk;
input	            i_rst_n;
	            
input  [63:0]		iv_command_ack_reg;
input               i_command_ack_reg_wr;
input  [63:0]       iv_command_ack_tab;
input               i_command_ack_tab_wr;
                             
output  reg         o_command_ack_wr;
output  reg   [63:0]ov_command_ack;
				

always@	(posedge i_clk or negedge i_rst_n)begin
	if(!i_rst_n) begin
		o_command_ack_wr	<= 1'b0;
		ov_command_ack	    <=64'b0;
	end
	else begin
	    if(i_command_ack_reg_wr)begin
			o_command_ack_wr	<=i_command_ack_reg_wr;
			ov_command_ack	    <=iv_command_ack_reg  ;		
		end
		else if(i_command_ack_tab_wr)begin 
			o_command_ack_wr	<=i_command_ack_tab_wr;
			ov_command_ack	    <=iv_command_ack_tab  ;			
		end
		else begin 
			o_command_ack_wr	<= 1'b0;
			ov_command_ack	    <=64'b0;		
		end
	end		
end
endmodule 